Deep si hole etching technique for super chip integration

H. Kurino, T. Fukushima, H. Kikuchi, H. Kijima, Y. Yamada, J. Shim, M. Koyanagi

Research output: Contribution to conferencePaperpeer-review

Abstract

In this paper, we have proposed super chip integration as future novel integration technology. We successfully demonstrated the technique of the deep hole etching on die glued with wafer as a unit process for super chip integration.

Original languageEnglish
Pages364-366
Number of pages3
Publication statusPublished - 2004 Dec 1
Event3rd International Conference on Semiconductor Technology, ISTC2004 - Shanghai, China
Duration: 2004 Sep 152004 Sep 17

Other

Other3rd International Conference on Semiconductor Technology, ISTC2004
CountryChina
CityShanghai
Period04/9/1504/9/17

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Deep si hole etching technique for super chip integration'. Together they form a unique fingerprint.

Cite this