Deep si hole etching technique for super chip integration

H. Kurino; T. Fukushima; H. Kikuchi; H. Kijima; Y. Yamada; J. Shim; M. Koyanagi

Deep si hole etching technique for super chip integration

H. Kurino, T. Fukushima, H. Kikuchi, H. Kijima, Y. Yamada, J. Shim, M. Koyanagi

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper, we have proposed super chip integration as future novel integration technology. We successfully demonstrated the technique of the deep hole etching on die glued with wafer as a unit process for super chip integration.

Original language	English
Pages	364-366
Number of pages	3
Publication status	Published - 2004 Dec 1
Event	3rd International Conference on Semiconductor Technology, ISTC2004 - Shanghai, China Duration: 2004 Sep 15 → 2004 Sep 17

Other

Other	3rd International Conference on Semiconductor Technology, ISTC2004
Country/Territory	China
City	Shanghai
Period	04/9/15 → 04/9/17

ASJC Scopus subject areas

Engineering(all)

Cite this

@conference{d36763e855934a6e8c8b64432157aa25,

title = "Deep si hole etching technique for super chip integration",

abstract = "In this paper, we have proposed super chip integration as future novel integration technology. We successfully demonstrated the technique of the deep hole etching on die glued with wafer as a unit process for super chip integration.",

author = "H. Kurino and T. Fukushima and H. Kikuchi and H. Kijima and Y. Yamada and J. Shim and M. Koyanagi",

year = "2004",

month = dec,

day = "1",

language = "English",

pages = "364--366",

note = "3rd International Conference on Semiconductor Technology, ISTC2004 ; Conference date: 15-09-2004 Through 17-09-2004",

}

TY - CONF

T1 - Deep si hole etching technique for super chip integration

AU - Kurino, H.

AU - Fukushima, T.

AU - Kikuchi, H.

AU - Kijima, H.

AU - Yamada, Y.

AU - Shim, J.

AU - Koyanagi, M.

PY - 2004/12/1

Y1 - 2004/12/1

N2 - In this paper, we have proposed super chip integration as future novel integration technology. We successfully demonstrated the technique of the deep hole etching on die glued with wafer as a unit process for super chip integration.

AB - In this paper, we have proposed super chip integration as future novel integration technology. We successfully demonstrated the technique of the deep hole etching on die glued with wafer as a unit process for super chip integration.

UR - http://www.scopus.com/inward/record.url?scp=28844465817&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=28844465817&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:28844465817

SP - 364

EP - 366

T2 - 3rd International Conference on Semiconductor Technology, ISTC2004

Y2 - 15 September 2004 through 17 September 2004

ER -

Deep si hole etching technique for super chip integration

Abstract

Other

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this