Cache memories are extensively used to reduce memory latency and memory bus traffic. This paper presents a cache memory control mechanism, called Decoupled Modified-bit Cache (DMC), which manages the clean/modified state of cached data in units of bytes to further reduce the bus traffic. Unlike conventional cache memories, the DMC has modified-bit arrays that are separated from a cache tag memory, and uses the modified-bits on demand. The DMC allows a non-fetch allocation on a write miss, cache line fills and replacements in units of bytes, and eliminates unnecessary data transfers. Our simulations with uni-processor and multiprocessor applications indicate that, with 3% more hardware, the DMC reduces the bus traffic and the number of transactions to between 10% and 40% of the levels in a conventional write-back cache memory. It also has strong potential for use in bus-interconnected multiprocessor systems, where the bus traffic dominates the system performance.
|Number of pages||8|
|Journal||Conference Proceedings - International Phoenix Conference on Computers and Communications|
|Publication status||Published - 1996 Jan 1|
|Event||Proceedings of the 1996 IEEE 15th Annual International Phoenix Conference on Computers and Communications - Scottsdale, AZ, USA|
Duration: 1996 Mar 27 → 1996 Mar 29
ASJC Scopus subject areas
- Computer Science(all)