Decoupled modified-bit cache

Masafumi Takahashi, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura

Research output: Contribution to journalArticle


Cache memory not only allows one to decrease average memory access time, but also relieves bus traffic and decreases bus latency. In this paper, to further relieve bus traffic, a write-back cache memory (DMC, Decoupled Modified-bit Cache) is proposed that provides data modification at byte level. DMC supports selective write-back of only modified data to memory which contributes to further relief of bus traffic. To avoid considerable requirements for additional hardware in implementing DMC, a method is proposed to separate status bits that indicate data modification from the cache, allocating them as necessary. Benchmark tests with a variety of applications were performed to validate DMC. The results show that, with an additional 3% of the cache memory allocated as memory cells for status bits, memory usage intensity and data flow through the bus are reduced by about 35% and 10%, respectively, when compared to a conventional write-back cache.

Original languageEnglish
Pages (from-to)49-59
Number of pages11
JournalSystems and Computers in Japan
Issue number6
Publication statusPublished - 1997 Jun 15


  • Bus traffic
  • Cache memory
  • Modified bit
  • Working set
  • Write-back cache

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics

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