DC-current-free low-power A/D converter circuitry using dynamic latch comparators with divided-capacitance voltage reference

Koji Kotani, Tadashi Shibata, Tadahiro Ohmi

Research output: Contribution to journalConference article

7 Citations (Scopus)

Abstract

We have developed a new A/D converter architecture by applying the concept of Clocked-Neuron-MOS circuitry. It features no dc power dissipation at any component in the A/D converter. In this architecture a comparator employs dynamic latch and the reference voltage is generated by a capacitive voltage divider configuration. As a results, all components in the A/D converter have become purely dynamic in their operation, resulting in a dramatic reduction in the power dissipation. These techniques have been combined with a flash and a two-step flash mechanism, and extremely-low-power A/D converters have been developed. Test circuits were fabricated using standard double-polysilicon CMOS process with 3-μm rules. The basic performance has been confirmed by the measurement of test circuits as well as by HSPICE simulation.

Original languageEnglish
Pages (from-to)205-208
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
Publication statusPublished - 1996 Jan 1
EventProceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA
Duration: 1996 May 121996 May 15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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