Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Quantum Annealing (QA) is a classical probabilistic algorithm that provides a heuristic to find the globally optimal solution for a combinatorial optimization problem by using quantum tunneling processes. Quantum annealing simulation can be implemented on Field Programmable Gate Arrays (FPGAs) using Quantum Monte Carlo (QMC) simulation in the transverse Ising model. Since input data of the QMC simulation increases exponentially with the problem size, we have to use the DRAM of an FPGA board to store these data. However, storing data in DRAM causes two problems. One is the limited data access bandwidth, and the other is the limitation of DRAM capacity. We propose a data-transfer-bottleneck-less FPGA-based accelerator for quantum annealing simulation and apply it to implement number partitioning problem, which is one of the combinatorial optimization problems. The critical idea of our architecture is not storing but computing the large data in FPGA kernels and eliminating the burden on data transfer. We implement the proposed architecture on Stratix 10 FPGA and achieve up to 39.6 times speed-up compared to CPU-based quantum annealing simulation. We also achieve up to 2.8 times speed-up and implement 262,144 spins, which is 64 times increase compared to the most recent FPGA implementation.

Original languageEnglish
Title of host publicationProceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages164-170
Number of pages7
ISBN (Electronic)9781728147253
DOIs
Publication statusPublished - 2019 Nov
Event7th International Symposium on Computing and Networking, CANDAR 2019 - Nagasaki, Japan
Duration: 2019 Nov 262019 Nov 29

Publication series

NameProceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019

Conference

Conference7th International Symposium on Computing and Networking, CANDAR 2019
CountryJapan
CityNagasaki
Period19/11/2619/11/29

Keywords

  • Data transfer-bottleneck
  • FPGA
  • Heterogeneous computing
  • OpenCL design
  • Simulated Quantum Annealing

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Networks and Communications
  • Hardware and Architecture
  • Signal Processing

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