Abstract
For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAS with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.
Original language | English |
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Pages (from-to) | 2658-2669 |
Number of pages | 12 |
Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
Volume | E98A |
Issue number | 12 |
DOIs | |
Publication status | Published - 2015 Dec |
Keywords
- Custom accelerators
- FPGA
- Heterogeneous multicore
- Reconfigurable architecture
ASJC Scopus subject areas
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics