Data retention time in DRAM with WSix/P+ poly-Si gate NMOS cell transistors

Hiroshi Kujirai; Kiyonori Ohyu; Masahiro Moniwa; Hideaki Kato; Kiyoshi Nakai; Hidetoshi Iwai; Mitsuo Nanba; Atsushi Ogishima

Data retention time in DRAM with WSix/P⁺ poly-Si gate NMOS cell transistors

Hiroshi Kujirai, Kiyonori Ohyu, Masahiro Moniwa, Hideaki Kato, Kiyoshi Nakai, Hidetoshi Iwai, Mitsuo Nanba, Atsushi Ogishima

Research output: Contribution to journal › Conference article › peer-review

5 Citations (Scopus)

Abstract

A 64-Mbit DRAM with WSix/P⁺poly-Si gate NMOS cell transistors (P+gate DRAM) has been developed to improve the DRAM data retention time of tail-distribution. The data retention time that corresponds to 0.01% failure bit in the cumulative probability of P+gate DRAM is 2.7 times longer than that of conventional N+gate DRAM. The main reason for improving data retention time is that low channel-doping level, which is achieved by P+gate DRAM, reduces the electric field at around 0.04um depth below the surface.

Original language	English
Pages (from-to)	395-398
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 2001 Dec 1
Event	IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States Duration: 2001 Dec 2 → 2001 Dec 5

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "Data retention time in DRAM with WSix/P+ poly-Si gate NMOS cell transistors",

abstract = "A 64-Mbit DRAM with WSix/P+poly-Si gate NMOS cell transistors (P+gate DRAM) has been developed to improve the DRAM data retention time of tail-distribution. The data retention time that corresponds to 0.01% failure bit in the cumulative probability of P+gate DRAM is 2.7 times longer than that of conventional N+gate DRAM. The main reason for improving data retention time is that low channel-doping level, which is achieved by P+gate DRAM, reduces the electric field at around 0.04um depth below the surface.",

author = "Hiroshi Kujirai and Kiyonori Ohyu and Masahiro Moniwa and Hideaki Kato and Kiyoshi Nakai and Hidetoshi Iwai and Mitsuo Nanba and Atsushi Ogishima",

year = "2001",

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language = "English",

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journal = "Technical Digest - International Electron Devices Meeting",

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note = "IEEE International Electron Devices Meeting IEDM 2001 ; Conference date: 02-12-2001 Through 05-12-2001",

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TY - JOUR

T1 - Data retention time in DRAM with WSix/P+ poly-Si gate NMOS cell transistors

AU - Kujirai, Hiroshi

AU - Ohyu, Kiyonori

AU - Moniwa, Masahiro

AU - Kato, Hideaki

AU - Nakai, Kiyoshi

AU - Iwai, Hidetoshi

AU - Nanba, Mitsuo

AU - Ogishima, Atsushi

PY - 2001/12/1

Y1 - 2001/12/1

N2 - A 64-Mbit DRAM with WSix/P+poly-Si gate NMOS cell transistors (P+gate DRAM) has been developed to improve the DRAM data retention time of tail-distribution. The data retention time that corresponds to 0.01% failure bit in the cumulative probability of P+gate DRAM is 2.7 times longer than that of conventional N+gate DRAM. The main reason for improving data retention time is that low channel-doping level, which is achieved by P+gate DRAM, reduces the electric field at around 0.04um depth below the surface.

AB - A 64-Mbit DRAM with WSix/P+poly-Si gate NMOS cell transistors (P+gate DRAM) has been developed to improve the DRAM data retention time of tail-distribution. The data retention time that corresponds to 0.01% failure bit in the cumulative probability of P+gate DRAM is 2.7 times longer than that of conventional N+gate DRAM. The main reason for improving data retention time is that low channel-doping level, which is achieved by P+gate DRAM, reduces the electric field at around 0.04um depth below the surface.

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M3 - Conference article

AN - SCOPUS:0035718111

SN - 0163-1918

SP - 395

EP - 398

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting IEDM 2001

Y2 - 2 December 2001 through 5 December 2001

ER -

Data retention time in DRAM with WSix/P⁺ poly-Si gate NMOS cell transistors

Abstract

ASJC Scopus subject areas

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