Data retention time in DRAM with WSix/P+ poly-Si gate NMOS cell transistors

Hiroshi Kujirai, Kiyonori Ohyu, Masahiro Moniwa, Hideaki Kato, Kiyoshi Nakai, Hidetoshi Iwai, Mitsuo Nanba, Atsushi Ogishima

    Research output: Contribution to journalConference articlepeer-review

    5 Citations (Scopus)


    A 64-Mbit DRAM with WSix/P+poly-Si gate NMOS cell transistors (P+gate DRAM) has been developed to improve the DRAM data retention time of tail-distribution. The data retention time that corresponds to 0.01% failure bit in the cumulative probability of P+gate DRAM is 2.7 times longer than that of conventional N+gate DRAM. The main reason for improving data retention time is that low channel-doping level, which is achieved by P+gate DRAM, reduces the electric field at around 0.04um depth below the surface.

    Original languageEnglish
    Pages (from-to)395-398
    Number of pages4
    JournalTechnical Digest - International Electron Devices Meeting
    Publication statusPublished - 2001 Dec 1
    EventIEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
    Duration: 2001 Dec 22001 Dec 5

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering
    • Materials Chemistry


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