Current and future three-dimensional LSI integration technology by "chip on chip", "chip on wafer" and "wafer on wafer"

Manabu Bonkohara, Makoto Motoyoshi, Kazutoshi Kamibayashi, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)


Recently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is represented by our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are five key technologies described. We consider the pros and cons of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer). We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

Original languageEnglish
Title of host publicationEnabling Technologies for 3-D Integration
Number of pages11
Publication statusPublished - 2007 Jun 29
Event2006 MRS Fall Meeting - Boston, MA, United States
Duration: 2006 Nov 272006 Nov 29

Publication series

NameMaterials Research Society Symposium Proceedings
ISSN (Print)0272-9172


Other2006 MRS Fall Meeting
Country/TerritoryUnited States
CityBoston, MA

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering


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