The behaviors of Cu diffusion at backside surface of thinned wafer with extrinsic gettering layer in three-dimensional (3-D) LSI were electrically and quantitatively evaluated by capacitance-time (C-t) analysis and Zerbst plot. In order to electrically evaluate Cu diffusion characteristics, MOS capacitors were fabricated using the thinned wafer of 100-m thickness. To compare the gettering ability to Cu diffusion, three types of extrinsic gettering layers were prepared on the back surface of thinned wafers by mechanical grinding and following CMP, DP, and UPG methods. For accelerated Cu diffusion test, thin Cu layer was deposited on the back surface as a contamination source and Cu atoms were artificially diffused into the substrate by annealing at 300C for various times. In the CMP treated wafer, the C-t curves of MOS capacitor are most severely degraded and transient time tf is more seriously decreased after annealing. The gettering efficiency of the DP treated wafer is enhanced about 50 as compared with the CMP treated wafer and 20 as compared with the UPG treated wafer, respectively, after annealing for 60 min. The DP treated wafer shows most good gettering ability to Cu diffusion.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Renewable Energy, Sustainability and the Environment
- Surfaces, Coatings and Films
- Materials Chemistry