This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) or carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based design and analysis of carry-propagation-free adders using redundant number representation.
|Number of pages||8|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2003 Jul 21|
|Event||Thirty-third International Symposium on Multiple-Valued Logic - Tokyo, Japan|
Duration: 2003 May 16 → 2003 May 19
ASJC Scopus subject areas
- Computer Science(all)