Counter tree diagrams - A unified representation of fast addition algorithms

Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper proposes a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs), which are useful for designing high-performance arithmetic circuits including non-binary arithmetic circuits. By using CTDs, one can describe and analyze arbitrary adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures considered in this paper include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also presents an application of CTDs to the design of fast adders with limited carry propagation. A possibility of CTD-based synthesis of arithmetic circuits is suggested.

Original languageEnglish
Pages (from-to)87-108
Number of pages22
JournalJournal of Multiple-Valued Logic and Soft Computing
Volume9
Issue number1 SPEC. ISS.
Publication statusPublished - 2003 Dec 1

Keywords

  • Circuit synthesis
  • Computer arithmetic algorithms
  • Datapath
  • Multipliers
  • Parallel counters
  • VLSI

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Logic

Fingerprint Dive into the research topics of 'Counter tree diagrams - A unified representation of fast addition algorithms'. Together they form a unique fingerprint.

  • Cite this