Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms

Jun Sakiyama, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)


This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based analysis of carry-propagation-free adders using various number representations.

Original languageEnglish
Pages (from-to)3009-3019
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number12
Publication statusPublished - 2003 Dec


  • Circuit synthesis
  • Computer arithmetic algorithms
  • Datapath
  • Multipliers
  • Parallel counters
  • VLSI

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


Dive into the research topics of 'Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms'. Together they form a unique fingerprint.

Cite this