Low VtNi fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large Vt shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The Vt shifts are preserved down to the shortest gate lengths. For both Al and Yb, the Vt shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low Vt dual implantation approach proposed achieves a low-cost "dual dielectric " implementation without the need of dual deposition dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-κ dielectric. The Yb diffusion and reaction at the interface can be engineered using a P coimplant.
- CMOS integration
- Dopant engineering
- Full silicidation
- Phase engineering
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering