Correlation between grain size and device parameters in pentacene thin film transistors

S. D. Wang, T. Miyadera, T. Minari, Y. Aoyagi, K. Tsukagoshi

Research output: Contribution to journalArticlepeer-review

96 Citations (Scopus)

Abstract

We develop a general approach to precisely extract the device parameters in top-contact pentacene thin film transistors. The charge trap sites are clarified by analyzing the grain size dependence of the device parameters. The channel mobility and threshold voltage are limited by the charge traps in the channel region, most of which are located not at the grain boundaries but at the organic/insulating-layer interface. The contact resistance decreases by increasing the grain size and is controlled by the charge traps in the contact region, which are suggested to be concentrated at the grain boundaries and at the metal/organic interface.

Original languageEnglish
Article number043311
JournalApplied Physics Letters
Volume93
Issue number4
DOIs
Publication statusPublished - 2008
Externally publishedYes

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

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