Configuration memory size reduction of a dynamically reconfigurable processor based on a register-transfer-level packet data transfer scheme

Yoshichika Fujioka, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A register-transfer-level packet routing scheme is proposed to reduce a configuration memory size of a Dynamically Reconfigurable Processor (DRP). The RT(Register-Transfer)-driven concept makes the configuration memory size very small, because packets are not required to be provided at all the clock cycles. Buffer-less routers can be used to construct a compact DRP, if offline scheduling/allocation is effectively utilized to avoid packet collision. Dynamic reconfiguration of Local Memories (LMs) is also realized by the packet data transfer control. It is evaluated that the packet-routing configuration memory size can be reduced to about 1/10 under the Functional Unit (FU) utilization ratio of 10% in comparison with the conventional DRP.

Original languageEnglish
Title of host publicationISOCC 2012 - 2012 International SoC Design Conference
Pages235-238
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of
Duration: 2012 Nov 42012 Nov 7

Publication series

NameISOCC 2012 - 2012 International SoC Design Conference

Other

Other2012 International SoC Design Conference, ISOCC 2012
CountryKorea, Republic of
CityJeju Island
Period12/11/412/11/7

Keywords

  • configuration memory
  • dynamic reconfiguration of local memories
  • dynamically reconfigurable processor
  • register-transfer-level packet transfer
  • semi-autonomous packet routing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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