Collision detection VLSI processor for intelligent vehicles based on efficient coordinate transformation scheme

Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)

Abstract

This paper describes a high-performance VLSI processor for the collision detection of intelligent vehicles. In the collision detection, high-computational power is essential in not only coordinate transformation but also matching operation between vehicle and obstacle pixels. In the processor, a content-addressable memory is introduced to store vehicle pixel information, so that the matching operation is drastically accelerated. Since vehicle pixel information is predetermined and not changed, the high-performance CAM based on a ROM cell is proposed. A parallel and pipelined architecture for the high-speed coordinate transformation is also proposed based on two-dimensional vector rotations and matrix multiplications.

Original languageEnglish
Pages755-760
Number of pages6
Publication statusPublished - 1996 Dec 1
EventProceedings of the 1996 IEEE 22nd International Conference on Industrial Electronics, Control, and Instrumentation, IECON. Part 2 (of 3) - Taipei, Taiwan
Duration: 1996 Aug 51996 Aug 10

Other

OtherProceedings of the 1996 IEEE 22nd International Conference on Industrial Electronics, Control, and Instrumentation, IECON. Part 2 (of 3)
CityTaipei, Taiwan
Period96/8/596/8/10

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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