Collision detection VLSI processor for intelligent vehicles based on ROM-Type content-addressable memory

Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

Abstract

In order to avoid dangerous situations, it is useful to check the possibility of collision between a vehicle and an obstacle at high speed. Serious problems of collision detection have been the tremendous processing time in matching the spaces occupied by the vehicle and the obstacle, and also in the coordinate transformation. This paper proposes a VLSI processor, where highly parallel matching is executed by fixed memorization of the space coordinate data of the vehicle in content-addressable memory (CAM). It is noted that real-time rewriting of the CAM memory content is not needed and it is shown that a high performance system can be realized by using a new read-only dedicated CAM based on ROM cells. A new parallel and pipelined architecture is proposed for the high-speed coordinate transformation, using the CORDIC algorithm.

Original languageEnglish
Pages (from-to)62-69
Number of pages8
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume80
Issue number5
DOIs
Publication statusPublished - 1997 May

Keywords

  • Content addressable memory
  • Dedicated VLSI processor
  • Parallel processing
  • Pipelined CORDIC architecture

ASJC Scopus subject areas

  • Physics and Astronomy(all)
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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