For safe driving, it is essential to defect collision between a vehicle and obstacles at high speed. In the collision detection, a large memory capacity is usually required to store 3-dimensional obstacle information. Moreover, high-computational power is required to perform the matching operation between vehicle and obstacle pixels. In the proposed multiprocessor, a new compact obstacle representation based on a union of rectangular solids is introduced, so that the matching operation is drastically accelerated by using a content-addressable memory(CAM) which evaluates magnitude relationships between an input word and all the stored words in parallel. Moreover, multiple-valued logic is used to implement a high-speed large-capacity CAM. The multiprocessor is constructed by several identical VLSI processors. The collision detection is performed in parallel by the VLSI processors without any communication between them, so that a desired performance can be achieved unless there is limitation on the number of the VLSI processors. For an example, a collision warning system for a maximum running speed of 36 km/h can be constructed with 100 VLSI processors.
|Number of pages||6|
|Publication status||Published - 1994 Dec 1|
|Event||Proceedings of the Intelligent Vehicles'94 Symposium - Paris, Fr|
Duration: 1994 Oct 24 → 1994 Oct 26
|Other||Proceedings of the Intelligent Vehicles'94 Symposium|
|Period||94/10/24 → 94/10/26|
ASJC Scopus subject areas