CMOS-Compatible Bipolar and I2L Technology Using Three-Level Epitaxial Layers for Analog/ Digital VLSI's

Katsuyoshi Washio, Yutaka Okada, Takahiro Okabe

Research output: Contribution to journalArticlepeer-review

Abstract

A high-performance bipolar/I2L/CMOS OnChip technology has been developed. To combine all devices, three-level epitaxial layers were used. Both n-p-n and lateral p-n-p bipolar transistors, and p-channel MOSFET's were fabricated on the top level epitaxial layer. I2L and n-channel MOSFET's were fabricated on the middle and bottom levels, respectively. Using a thin epitaxial layer and simultaneously reducing the level of regions for n-channel MOSFET's and bipolar isolation grooves, the process sequence was designed to be as simple as possible. Bipolar n-p-n transistors with a maximum cutoff frequency of 5 GHz, I2L circuits having 40-MHz maximum toggle frequency, and CMOS devices operating at a minimum propagation delay time of 300 ps/gate were developed compatibly. This technology has feasibility for application to multifunctional analog/digital VLSI's.

Original languageEnglish
Pages (from-to)1708-1712
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume34
Issue number8
DOIs
Publication statusPublished - 1987 Aug
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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