Clockless stochastic decoding of low-density parity-check codes: Architecture and simulation model

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)

Abstract

This paper introduces clockless stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-lowcomplexity hardware using simple logic gates. Clockless decoding eliminates global clocking, which eases the worstcase timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes; however, it does not significantly affect output probabilities. A timing model of clockless-computation behaviours under a 90 nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the "lock-up" problem and achieves superior BER performance compared with conventional synchronous stochastic decoders. The timing model includes metastability to verify the affect on BER performance.

Original languageEnglish
Pages (from-to)185-194
Number of pages10
JournalJournal of Signal Processing Systems
Volume76
Issue number2
DOIs
Publication statusPublished - 2014 Aug

Keywords

  • Circuit implementation
  • Clockless computation
  • Forward error correction codes
  • Iterative decoding
  • Stochastic computation

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modelling and Simulation
  • Hardware and Architecture

Fingerprint

Dive into the research topics of 'Clockless stochastic decoding of low-density parity-check codes: Architecture and simulation model'. Together they form a unique fingerprint.

Cite this