Clockless stochasic decoding of low-density parity-check codes

Naoya Onizawa; W. J. Gross; Takahiro Hanyu; V. C. Gaudet

doi:10.1109/SiPS.2012.53

Clockless stochasic decoding of low-density parity-check codes

Naoya Onizawa, W. J. Gross, Takahiro Hanyu, V. C. Gaudet

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

This paper introduces clockless stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clockless decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes; however, it does not significantly affect output probabilities. A timing model of clockless-computation behaviours under a 90nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the "lock-up" problem and achieves superior BER performance compared with conventional synchronous stochastic decoders.

Original language	English
Title of host publication	Proceedings - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
Pages	143-148
Number of pages	6
DOIs	https://doi.org/10.1109/SiPS.2012.53
Publication status	Published - 2012 Dec 1
Event	2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 - Quebec City, QC, Canada Duration: 2012 Oct 17 → 2012 Oct 19

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)	1520-6130

Other

Other	2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
Country	Canada
City	Quebec City, QC
Period	12/10/17 → 12/10/19

Keywords

Circuit implementation
Clockless computation
Forward error correction codes
Iterative decoding
Stochastic computation

ASJC Scopus subject areas

Electrical and Electronic Engineering
Signal Processing
Applied Mathematics
Hardware and Architecture

Access to Document

10.1109/SiPS.2012.53

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Cite this

Clockless stochasic decoding of low-density parity-check codes. / Onizawa, Naoya; Gross, W. J.; Hanyu, Takahiro; Gaudet, V. C.

Proceedings - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012. 2012. p. 143-148 6363197 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Onizawa, N, Gross, WJ, Hanyu, T & Gaudet, VC 2012, Clockless stochasic decoding of low-density parity-check codes. in Proceedings - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012., 6363197, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, pp. 143-148, 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012, Quebec City, QC, Canada, 12/10/17. https://doi.org/10.1109/SiPS.2012.53

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