TY - GEN
T1 - Clockless stochasic decoding of low-density parity-check codes
AU - Onizawa, N.
AU - Gross, W. J.
AU - Hanyu, T.
AU - Gaudet, V. C.
PY - 2012/12/1
Y1 - 2012/12/1
N2 - This paper introduces clockless stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clockless decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes; however, it does not significantly affect output probabilities. A timing model of clockless-computation behaviours under a 90nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the "lock-up" problem and achieves superior BER performance compared with conventional synchronous stochastic decoders.
AB - This paper introduces clockless stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clockless decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes; however, it does not significantly affect output probabilities. A timing model of clockless-computation behaviours under a 90nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the "lock-up" problem and achieves superior BER performance compared with conventional synchronous stochastic decoders.
KW - Circuit implementation
KW - Clockless computation
KW - Forward error correction codes
KW - Iterative decoding
KW - Stochastic computation
UR - http://www.scopus.com/inward/record.url?scp=84875299212&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84875299212&partnerID=8YFLogxK
U2 - 10.1109/SiPS.2012.53
DO - 10.1109/SiPS.2012.53
M3 - Conference contribution
AN - SCOPUS:84875299212
SN - 9780769548562
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 143
EP - 148
BT - Proceedings - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
T2 - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
Y2 - 17 October 2012 through 19 October 2012
ER -