Clockless stochasic decoding of low-density parity-check codes

Naoya Onizawa, W. J. Gross, Takahiro Hanyu, V. C. Gaudet

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper introduces clockless stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clockless decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes; however, it does not significantly affect output probabilities. A timing model of clockless-computation behaviours under a 90nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the "lock-up" problem and achieves superior BER performance compared with conventional synchronous stochastic decoders.

Original languageEnglish
Title of host publicationProceedings - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
Pages143-148
Number of pages6
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 - Quebec City, QC, Canada
Duration: 2012 Oct 172012 Oct 19

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
CountryCanada
CityQuebec City, QC
Period12/10/1712/10/19

Keywords

  • Circuit implementation
  • Clockless computation
  • Forward error correction codes
  • Iterative decoding
  • Stochastic computation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

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