A new clocked vMOS logic circuit scheme is presented in which a clock-driven switching transistor attached to the floating gate is used not only to initialize the floating-gate charge but also to perform auto-adjusting of its inverting threshold that cancels the fluctuations arising from fabrication.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 1995 Feb 1|
|Event||Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA|
Duration: 1995 Feb 15 → 1995 Feb 17
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering