Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment

Koji Kotani, Tadashi Shibata, Makoto Imai, Tadahiro Ohmi

Research output: Contribution to journalConference articlepeer-review

85 Citations (Scopus)


A new clocked vMOS logic circuit scheme is presented in which a clock-driven switching transistor attached to the floating gate is used not only to initialize the floating-gate charge but also to perform auto-adjusting of its inverting threshold that cancels the fluctuations arising from fabrication.

Original languageEnglish
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 1995 Feb 1
EventProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1995 Feb 151995 Feb 17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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