TY - JOUR
T1 - Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices
AU - Suzuki, Daisuke
AU - Oka, Takahiro
AU - Hanyu, Takahiro
N1 - Funding Information:
This research is supported by ImPACT of CSTI, JST-OPERA, and Industry-Academic collaboration of CIES consortium.
Funding Information:
This research is supported by ImPACT of CSTI , JST-OPERA , and Industry-Academic collaboration of CIES consortium.
Publisher Copyright:
© 2018 Elsevier Ltd
PY - 2019/1
Y1 - 2019/1
N2 - A circuit optimization technique of nonvolatile logic-in-memory (NVLIM)-based lookup table (LUT) circuits in conjunction with magnetic-tunnel junction (MTJ) devices is proposed. Three important points should be considered for the circuit optimization technique of the NVLIM-based LUT circuit. One is optimizing DC and transient characteristics of the read current path, another is minimizing the effect of capacitance of both read-access transistors and write-access transistors, the other is how to design the selector circuit. As a typical example, the NVLIM-based LUT circuits is designed using 55 nm CMOS technology with two types of MTJ devices; the output delay, power and area of the circuit are evaluated. As a result, the output delay in the NVLIM-based 6-input LUT circuit is reduced by 47% compared to that of conventional SRAM-based implementation with 27% lower active power consumption as well as 67% of area reduction.
AB - A circuit optimization technique of nonvolatile logic-in-memory (NVLIM)-based lookup table (LUT) circuits in conjunction with magnetic-tunnel junction (MTJ) devices is proposed. Three important points should be considered for the circuit optimization technique of the NVLIM-based LUT circuit. One is optimizing DC and transient characteristics of the read current path, another is minimizing the effect of capacitance of both read-access transistors and write-access transistors, the other is how to design the selector circuit. As a typical example, the NVLIM-based LUT circuits is designed using 55 nm CMOS technology with two types of MTJ devices; the output delay, power and area of the circuit are evaluated. As a result, the output delay in the NVLIM-based 6-input LUT circuit is reduced by 47% compared to that of conventional SRAM-based implementation with 27% lower active power consumption as well as 67% of area reduction.
KW - Circuit optimization
KW - Field-programmable gate array
KW - Lookup-table circuit
KW - Magnetic tunnel junction device
UR - http://www.scopus.com/inward/record.url?scp=85057564961&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85057564961&partnerID=8YFLogxK
U2 - 10.1016/j.mejo.2018.10.013
DO - 10.1016/j.mejo.2018.10.013
M3 - Article
AN - SCOPUS:85057564961
VL - 83
SP - 39
EP - 49
JO - Microelectronics
JF - Microelectronics
SN - 0026-2692
ER -