Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

More recently, "chiplets"are expected for further scaling the performance of LSI systems. However, system integration with the chiplets is not a new methodology. The basic concept dates back well over a few decades. The symbolic configuration of this concept based on the chiplets is 3D integration with TSV we have worked on since 1989. This paper introduces our 3D and heterogeneous system integration research from its historical activities to the latest efforts, including capillary self-assembly of tiny dies with a size of less than 0.1 mm and advanced flexible hybrid electronics (FHE) using fan-out wafer-level packaging (FOWLP).

Original languageEnglish
Title of host publication2021 Symposium on VLSI Circuits, VLSI Circuits 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487796
DOIs
Publication statusPublished - 2021 Jun 13
Event35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online
Duration: 2021 Jun 132021 Jun 19

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2021-June

Conference

Conference35th Symposium on VLSI Circuits, VLSI Circuits 2021
CityVirutal, Online
Period21/6/1321/6/19

Keywords

  • 3DIC
  • chiplet
  • FHE
  • FOWLP
  • self-assembly
  • TSV

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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