TY - GEN
T1 - Chip-to-chip/wafer three-dimensional integration of 2.5 mm-sized neuron and memory chips by via-last approach
AU - Murugesan, M.
AU - Hashimoto, H.
AU - Bea, Jichel
AU - Koyanagi, M.
AU - Fukushima, T.
N1 - Funding Information:
This paper is based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO).
Publisher Copyright:
© 2021 IEEE
PY - 2021/10/5
Y1 - 2021/10/5
N2 - A low thermal budget (= 250 °C) chip-to-chip and chip-to-wafer three-dimensional (3D) integration of application-specific smaller artificial intelligence (AI) chips (2.5 mm x 2.5 mm) with 6 level metal (M#) layers were carried out by using TSV (Through - Si - Via) - last method. Several back-end-of-line processes were carefully optimized, such as multi-die thinning, Ml revealing, protection of revealed Ml during TSV metallization, die-level Cu-chemical mechanical polishing for re-distribution layer formation, and µ-bumping were carefully optimized. The diode parameter evaluation for the chips before and after 3D-integration revealed the successful fabrication of AI module for specific applications.
AB - A low thermal budget (= 250 °C) chip-to-chip and chip-to-wafer three-dimensional (3D) integration of application-specific smaller artificial intelligence (AI) chips (2.5 mm x 2.5 mm) with 6 level metal (M#) layers were carried out by using TSV (Through - Si - Via) - last method. Several back-end-of-line processes were carefully optimized, such as multi-die thinning, Ml revealing, protection of revealed Ml during TSV metallization, die-level Cu-chemical mechanical polishing for re-distribution layer formation, and µ-bumping were carefully optimized. The diode parameter evaluation for the chips before and after 3D-integration revealed the successful fabrication of AI module for specific applications.
UR - http://www.scopus.com/inward/record.url?scp=85120404442&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85120404442&partnerID=8YFLogxK
U2 - 10.1109/LTB-3D53950.2021.9598372
DO - 10.1109/LTB-3D53950.2021.9598372
M3 - Conference contribution
AN - SCOPUS:85120404442
T3 - 2021 7th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2021
SP - 28
BT - 2021 7th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2021
Y2 - 5 October 2021 through 11 October 2021
ER -