TY - GEN
T1 - Chip-level TSV integration for rapid prototyping of 3D system LSIs
AU - Hozawa, Kazuyuki
AU - Furuta, Futoshi
AU - Hanaoka, Yuko
AU - Aoki, Mayu
AU - Takeda, Kenichi
AU - Sakuma, Katsuyuki
AU - Ri, Kanuku
AU - Fukushima, Takafumi
AU - Koyanagi, Mitsumasa
PY - 2011/12/1
Y1 - 2011/12/1
N2 - For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.
AB - For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.
UR - http://www.scopus.com/inward/record.url?scp=84866877386&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84866877386&partnerID=8YFLogxK
U2 - 10.1109/3DIC.2012.6262952
DO - 10.1109/3DIC.2012.6262952
M3 - Conference contribution
AN - SCOPUS:84866877386
SN - 9781467321891
T3 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
BT - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
T2 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Y2 - 31 January 2012 through 2 February 2012
ER -