Chip-level TSV integration for rapid prototyping of 3D system LSIs

Kazuyuki Hozawa; Futoshi Furuta; Yuko Hanaoka; Mayu Aoki; Kenichi Takeda; Katsuyuki Sakuma; Kanuku Ri; Takafumi Fukushima; Mitsumasa Koyanagi

doi:10.1109/3DIC.2012.6262952

Chip-level TSV integration for rapid prototyping of 3D system LSIs

Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kanuku Ri, Takafumi Fukushima, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

Original language	English
Title of host publication	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs	https://doi.org/10.1109/3DIC.2012.6262952
Publication status	Published - 2011 Dec 1
Event	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan Duration: 2012 Jan 31 → 2012 Feb 2

Publication series

Name	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Country/Territory	Japan
City	Osaka
Period	12/1/31 → 12/2/2

ASJC Scopus subject areas

Control and Systems Engineering

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10.1109/3DIC.2012.6262952

Cite this

Hozawa, K., Furuta, F., Hanaoka, Y., Aoki, M., Takeda, K., Sakuma, K., Ri, K., Fukushima, T., & Koyanagi, M. (2011). Chip-level TSV integration for rapid prototyping of 3D system LSIs. In 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 [6262952] (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011). https://doi.org/10.1109/3DIC.2012.6262952

Chip-level TSV integration for rapid prototyping of 3D system LSIs. / Hozawa, Kazuyuki; Furuta, Futoshi; Hanaoka, Yuko et al.

2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. 2011. 6262952 (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hozawa, K, Furuta, F, Hanaoka, Y, Aoki, M, Takeda, K, Sakuma, K, Ri, K, Fukushima, T & Koyanagi, M 2011, Chip-level TSV integration for rapid prototyping of 3D system LSIs. in 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011., 6262952, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, Osaka, Japan, 12/1/31. https://doi.org/10.1109/3DIC.2012.6262952

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title = "Chip-level TSV integration for rapid prototyping of 3D system LSIs",

abstract = "For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called {"}chip-level TSV integration{"}) was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.",

author = "Kazuyuki Hozawa and Futoshi Furuta and Yuko Hanaoka and Mayu Aoki and Kenichi Takeda and Katsuyuki Sakuma and Kanuku Ri and Takafumi Fukushima and Mitsumasa Koyanagi",

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doi = "10.1109/3DIC.2012.6262952",

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AU - Hozawa, Kazuyuki

AU - Furuta, Futoshi

AU - Hanaoka, Yuko

AU - Aoki, Mayu

AU - Takeda, Kenichi

AU - Sakuma, Katsuyuki

AU - Ri, Kanuku

AU - Fukushima, Takafumi

AU - Koyanagi, Mitsumasa

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N2 - For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

AB - For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

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Chip-level TSV integration for rapid prototyping of 3D system LSIs

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