Chip-level TSV integration for rapid prototyping of 3D system LSIs

Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kanuku Ri, Takafumi Fukushima, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

Original languageEnglish
Title of host publication2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan
Duration: 2012 Jan 312012 Feb 2

Publication series

Name2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Country/TerritoryJapan
CityOsaka
Period12/1/3112/2/2

ASJC Scopus subject areas

  • Control and Systems Engineering

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