Chip level simulation of substrate noise coupling and interference in RF ICs with CMOS digital noise emulator

Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi

Research output: Contribution to journalArticlepeer-review


Substrate noise coupling in RF receiver front-end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65 nm CMOS technology. A CMOS digital noise emulator injects high-order harmonic noises in a silicon substrate and induces in-band spurious tones in an RF receiver on the same chip through substrate noise interference. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixedlevel simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compared with the measurements. The interference of substrate noise at the 17th harmonics of 124.8MHz-the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1 GHz.

Original languageEnglish
Pages (from-to)546-556
Number of pages11
JournalIEICE Transactions on Electronics
Issue number6
Publication statusPublished - 2014 Jun


  • Noise interference
  • Power delivery network
  • Substrate coupling
  • Wireless communication

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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