Chip-based hetero-integration technology for high-performance 3D stacked image sensor

Yuki Ohara, Kang Wook Lee, Koji Kiyoyama, Shigehide Konno, Yutaka Sato, Shuichi Watanabe, Atsushi Yabata, Harufumi Kobayashi, Tadashi Kamada, Jichel Bea, Mariappan Murugesan, Hiroyuki Hashimoto, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous integration technology. Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.

Original languageEnglish
Title of host publication2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012 - Kyoto, Japan
Duration: 2012 Dec 102012 Dec 12

Publication series

Name2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

Other

Other2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
CountryJapan
CityKyoto
Period12/12/1012/12/12

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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