TY - GEN
T1 - Chip-based hetero-integration technology for high-performance 3D stacked image sensor
AU - Ohara, Yuki
AU - Lee, Kang Wook
AU - Kiyoyama, Koji
AU - Konno, Shigehide
AU - Sato, Yutaka
AU - Watanabe, Shuichi
AU - Yabata, Atsushi
AU - Kobayashi, Harufumi
AU - Kamada, Tadashi
AU - Bea, Jichel
AU - Murugesan, Mariappan
AU - Hashimoto, Hiroyuki
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
AU - Koyanagi, Mitsumasa
PY - 2012/12/1
Y1 - 2012/12/1
N2 - We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous integration technology. Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
AB - We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous integration technology. Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
UR - http://www.scopus.com/inward/record.url?scp=84879760618&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84879760618&partnerID=8YFLogxK
U2 - 10.1109/ICSJ.2012.6523452
DO - 10.1109/ICSJ.2012.6523452
M3 - Conference contribution
AN - SCOPUS:84879760618
SN - 9781467326551
T3 - 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
BT - 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
T2 - 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
Y2 - 10 December 2012 through 12 December 2012
ER -