Charge trapping type SOI-FinFET flash memory

Y. X. Liu, T. Nabatame, T. Matsukawa, K. Endo, S. O'uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyow, M. Masahara

Research output: Contribution to journalConference articlepeer-review

3 Citations (Scopus)

Abstract

The charge trapping (CT) type tri-gate (TG) silicon on insulator (SOI) FinFET flash memories with different gate and blocking layer materials have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability and memory property have comparatively been investigated. It was experimentally found that a large memory window is obtained in the physical vapor deposited (PVD) titanium nitride (TiN) metal gate flash memories than the n+-poly-Si gate ones owing to the higher work function of PVD-TiN metal gate, which is effective to suppress electron back tunneling during erase operation. It was also confirmed that the better SCE immunity and a significant improvement in memory window are observed by introducing a high-k Al2O3 blocking layer into the PVD-TiN metal gate flash memories. Moreover, it was found that the Vt variations before and after a program/erase (P/E) cycle are independent of the gate and blocking layer materials.

Original languageEnglish
Pages (from-to)263-280
Number of pages18
JournalECS Transactions
Volume61
Issue number2
DOIs
Publication statusPublished - 2014 Jan 1
Externally publishedYes
Event6th International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 225th ECS Meeting - Orlando, United States
Duration: 2014 May 112014 May 15

ASJC Scopus subject areas

  • Engineering(all)

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