Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

K. W. Lee; Y. Ohara; K. Kiyoyama; S. Konno; Y. Sato; S. Watanabe; A. Yabata; T. Kamada; J. C. Bea; H. Hashimoto; M. Murugesan; T. Fukushima; T. Tanaka; M. Koyanagi

doi:10.1109/IEDM.2012.6479156

Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

K. W. Lee, Y. Ohara, K. Kiyoyama, S. Konno, Y. Sato, S. Watanabe, A. Yabata, T. Kamada, J. C. Bea, H. Hashimoto, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.

Original language	English
Title of host publication	2012 IEEE International Electron Devices Meeting, IEDM 2012
Pages	33.2.1-33.2.4
DOIs	https://doi.org/10.1109/IEDM.2012.6479156
Publication status	Published - 2012
Event	2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States Duration: 2012 Dec 10 → 2012 Dec 13

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2012 IEEE International Electron Devices Meeting, IEDM 2012
Country/Territory	United States
City	San Francisco, CA
Period	12/12/10 → 12/12/13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.2012.6479156

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Lee, K. W., Ohara, Y., Kiyoyama, K., Konno, S., Sato, Y., Watanabe, S., Yabata, A., Kamada, T., Bea, J. C., Hashimoto, H., Murugesan, M., Fukushima, T., Tanaka, T., & Koyanagi, M. (2012). Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system. In 2012 IEEE International Electron Devices Meeting, IEDM 2012 (pp. 33.2.1-33.2.4). [6479156] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2012.6479156

Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system. / Lee, K. W.; Ohara, Y.; Kiyoyama, K. et al.

2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. p. 33.2.1-33.2.4 6479156 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, KW, Ohara, Y, Kiyoyama, K, Konno, S, Sato, Y, Watanabe, S, Yabata, A, Kamada, T, Bea, JC, Hashimoto, H, Murugesan, M, Fukushima, T , Tanaka, T & Koyanagi, M 2012, Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system. in 2012 IEEE International Electron Devices Meeting, IEDM 2012., 6479156, Technical Digest - International Electron Devices Meeting, IEDM, pp. 33.2.1-33.2.4, 2012 IEEE International Electron Devices Meeting, IEDM 2012, San Francisco, CA, United States, 12/12/10. https://doi.org/10.1109/IEDM.2012.6479156

Lee KW, Ohara Y, Kiyoyama K, Konno S, Sato Y, Watanabe S et al. Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system. In 2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. p. 33.2.1-33.2.4. 6479156. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2012.6479156

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title = "Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system",

abstract = "We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.",

author = "Lee, {K. W.} and Y. Ohara and K. Kiyoyama and S. Konno and Y. Sato and S. Watanabe and A. Yabata and T. Kamada and Bea, {J. C.} and H. Hashimoto and M. Murugesan and T. Fukushima and T. Tanaka and M. Koyanagi",

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AU - Watanabe, S.

AU - Yabata, A.

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AB - We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.

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Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

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