TY - GEN
T1 - Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system
AU - Lee, K. W.
AU - Ohara, Y.
AU - Kiyoyama, K.
AU - Konno, S.
AU - Sato, Y.
AU - Watanabe, S.
AU - Yabata, A.
AU - Kamada, T.
AU - Bea, J. C.
AU - Hashimoto, H.
AU - Murugesan, M.
AU - Fukushima, T.
AU - Tanaka, T.
AU - Koyanagi, M.
PY - 2012
Y1 - 2012
N2 - We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
AB - We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
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U2 - 10.1109/IEDM.2012.6479156
DO - 10.1109/IEDM.2012.6479156
M3 - Conference contribution
AN - SCOPUS:84876007962
SN - 9781467348706
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 33.2.1-33.2.4
BT - 2012 IEEE International Electron Devices Meeting, IEDM 2012
T2 - 2012 IEEE International Electron Devices Meeting, IEDM 2012
Y2 - 10 December 2012 through 13 December 2012
ER -