Abstract
A 0.25-μm ferroelectric memory with 16 kbit-cell array was fabricated. A Pb(Zr, Ti)O3 (PZT) capacitor was formed on a metal(Al)/via(W)-stacked plug using low temperature metal organic chemical vapor deposition (MO-CVD). The backend process had no effect on the PZT capacitor properties. The 1 × 1 μm2 capacitor shows good fatigue and imprint endurance. Signal voltage on the bit-line in the cell array is 1.06 V for switching and 0.58 V for unswitching. These results agree well with the pulse-response measurement of the parallel capacitor. However, the signal voltage deviation becomes larger with the capacitor size reduction. The 16 kbit-cell array shows the column access time of 50 ns and the minimum operation voltage of 1.6 V.
| Original language | English |
|---|---|
| Pages (from-to) | 2098-2101 |
| Number of pages | 4 |
| Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| Volume | 39 |
| Issue number | 4 B |
| Publication status | Published - 2000 Dec 1 |
| Externally published | Yes |
Keywords
- Bit-line voltage
- Fatigue
- Ferroelectric
- Hysteresis
- Imprint
- Nonvolatile memory
- PZT
- Polarization
- Pulse response
ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)
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Amanuma, K., Kobayashi, S., Tatsumi, T., Maejima, Y., Hada, H., Yamada, J., Miwa, T., Koike, H., Toyoshima, H., & Kunio, T. (2000). Characteristics of 0.25 μm ferroelectric nonvolatile memory with a Pb(Zr, Ti)O3 capacitor on a metal/via-stacked plug. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 39(4 B), 2098-2101.