Channel profiles are clarified to obtain a low Vth and a high surface channel effects immunity of BC-PMOSFETs used in 4-Gbit DRAMs. Using B10H14 ion implantation technology and a low temperature process, a BC-PMOSFET with a 20-nm counter-doped layer is fabricated. A high performance 0.18-μm PMOSFET with a Vth of 0.2 V and an S-factor of 85 mV/dec is demonstrated. BC-PMOSFET can scale on n+ poly-Si gate CMOS to less than 0.18-μm, facilitating the fabrication of 4-Gbit DRAMs and beyond.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 1998 Jan 1|
|Event||Proceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA|
Duration: 1998 Jun 9 → 1998 Jun 11
ASJC Scopus subject areas
- Electrical and Electronic Engineering