Channel engineering using B10H14 ion implantation for low Vth and high SCE immunity of buried-channel PMOSFETs in 4-Gbit DRAMs and beyond

T. Tanaka, H. Ogawa, K. Goto, K. Itabashi, T. Yamazaki, J. Matsuo, T. Sugii, I. Yamada

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

Channel profiles are clarified to obtain a low Vth and a high surface channel effects immunity of BC-PMOSFETs used in 4-Gbit DRAMs. Using B10H14 ion implantation technology and a low temperature process, a BC-PMOSFET with a 20-nm counter-doped layer is fabricated. A high performance 0.18-μm PMOSFET with a Vth of 0.2 V and an S-factor of 85 mV/dec is demonstrated. BC-PMOSFET can scale on n+ poly-Si gate CMOS to less than 0.18-μm, facilitating the fabrication of 4-Gbit DRAMs and beyond.

Original languageEnglish
Pages (from-to)88-89
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 1998 Jan 1
Externally publishedYes
EventProceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 1998 Jun 91998 Jun 11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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