Challenges in 3D integration

Mitsumasa Koyanagi, Kanuku Ri, Takafumi Fukushima, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

Original languageEnglish
Title of host publicationSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3
Pages237-244
Number of pages8
Edition3
DOIs
Publication statusPublished - 2013 Oct 21
EventInternational Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 - 223rd ECS Meeting - Toronto, ON, Canada
Duration: 2013 May 122013 May 17

Publication series

NameECS Transactions
Number3
Volume53
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherInternational Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 - 223rd ECS Meeting
CountryCanada
CityToronto, ON
Period13/5/1213/5/17

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Koyanagi, M., Ri, K., Fukushima, T., & Tanaka, T. (2013). Challenges in 3D integration. In Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 (3 ed., pp. 237-244). (ECS Transactions; Vol. 53, No. 3). https://doi.org/10.1149/05303.0237ecst