TY - GEN
T1 - Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor
AU - Hanyu, Takahiro
PY - 2013/9/9
Y1 - 2013/9/9
N2 - A new logic-circuit style based on nonvolatile logic-in-memory architecture is proposed for realizing compact, low-power logic and highly reliable VLSI processors with parallel data accessibility. Since nonvolatile storage elements such as magnetic tunnel junction (MTJ) devices are distributed over a logic-circuit plane in the proposed style, wide memory bandwidth as well as instant power gating without escaping/reloading data can be realized. As typical examples, and an MTJ-based nonvolatile Ternary Content-Addressable Memory, an MTJ-based nonvolatile look-up table circuit for an instant power-ON/OFF field programmable gate array and a post-process variation-resilient logic-circuit design using MTJ devices are implemented and their superior performances are demonstrated in comparison with a corresponding CMOS-only-based realization.
AB - A new logic-circuit style based on nonvolatile logic-in-memory architecture is proposed for realizing compact, low-power logic and highly reliable VLSI processors with parallel data accessibility. Since nonvolatile storage elements such as magnetic tunnel junction (MTJ) devices are distributed over a logic-circuit plane in the proposed style, wide memory bandwidth as well as instant power gating without escaping/reloading data can be realized. As typical examples, and an MTJ-based nonvolatile Ternary Content-Addressable Memory, an MTJ-based nonvolatile look-up table circuit for an instant power-ON/OFF field programmable gate array and a post-process variation-resilient logic-circuit design using MTJ devices are implemented and their superior performances are demonstrated in comparison with a corresponding CMOS-only-based realization.
KW - field-programmable gate array (FPGA)
KW - magnetco-resistive RAM (MRAM)
KW - process-temperature-voltage (PVT) variation
KW - ternary content-addressable memory (TCAM)
UR - http://www.scopus.com/inward/record.url?scp=84883434273&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2013.6571796
DO - 10.1109/ISCAS.2013.6571796
M3 - Conference contribution
AN - SCOPUS:84883434273
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 117
EP - 120
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -