Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

A new logic-circuit style based on nonvolatile logic-in-memory architecture is proposed for realizing compact, low-power logic and highly reliable VLSI processors with parallel data accessibility. Since nonvolatile storage elements such as magnetic tunnel junction (MTJ) devices are distributed over a logic-circuit plane in the proposed style, wide memory bandwidth as well as instant power gating without escaping/reloading data can be realized. As typical examples, and an MTJ-based nonvolatile Ternary Content-Addressable Memory, an MTJ-based nonvolatile look-up table circuit for an instant power-ON/OFF field programmable gate array and a post-process variation-resilient logic-circuit design using MTJ devices are implemented and their superior performances are demonstrated in comparison with a corresponding CMOS-only-based realization.

Original languageEnglish
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages117-120
Number of pages4
DOIs
Publication statusPublished - 2013 Sep 9
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: 2013 May 192013 May 23

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
CountryChina
CityBeijing
Period13/5/1913/5/23

Keywords

  • field-programmable gate array (FPGA)
  • magnetco-resistive RAM (MRAM)
  • process-temperature-voltage (PVT) variation
  • ternary content-addressable memory (TCAM)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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