Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

Takahiro Hanyu; Masanori Natsui; Daisuke Suzuki; Akira Mochizuki; Naoya Onizawa; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno

doi:10.1109/S3S.2015.7333502

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

Takahiro Hanyu, Masanori Natsui, Daisuke Suzuki, Akira Mochizuki, Naoya Onizawa, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Novel logic-LSI architecture, 'nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

Original language	English
Title of host publication	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509002597
DOIs	https://doi.org/10.1109/S3S.2015.7333502
Publication status	Published - 2015 Nov 20
Event	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States Duration: 2015 Oct 5 → 2015 Oct 8

Publication series

Name	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Other

Other	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Country/Territory	United States
City	Rohnert Park
Period	15/10/5 → 15/10/8

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/S3S.2015.7333502

Cite this

Hanyu, T., Natsui, M., Suzuki, D., Mochizuki, A., Onizawa, N., Ikeda, S., Endoh, T., & Ohno, H. (2015). Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 [7333502] (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2015.7333502

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. / Hanyu, Takahiro ; Natsui, Masanori; Suzuki, Daisuke et al.

2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7333502 (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hanyu, T , Natsui, M, Suzuki, D, Mochizuki, A, Onizawa, N , Ikeda, S , Endoh, T & Ohno, H 2015, Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015., 7333502, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Institute of Electrical and Electronics Engineers Inc., IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Rohnert Park, United States, 15/10/5. https://doi.org/10.1109/S3S.2015.7333502

Hanyu T , Natsui M, Suzuki D, Mochizuki A, Onizawa N , Ikeda S et al. Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7333502. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). doi: 10.1109/S3S.2015.7333502

Hanyu, Takahiro ; Natsui, Masanori ; Suzuki, Daisuke et al. / Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

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abstract = "Novel logic-LSI architecture, 'nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.",

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AB - Novel logic-LSI architecture, 'nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

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Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

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