Challenge of a multiple-valued technology in recent deep-submicron VLSI

T. Hanyu

Challenge of a multiple-valued technology in recent deep-submicron VLSI

T. Hanyu

Systems & Software Division

Research output: Contribution to journal › Conference article › peer-review

5 Citations (Scopus)

Abstract

A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS passtransistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.

Original language	English
Pages (from-to)	241-244
Number of pages	4
Journal	Proceedings of The International Symposium on Multiple-Valued Logic
Publication status	Published - 2001 Jan 1
Event	31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001) - Warsaw, Poland Duration: 2001 May 22 → 2001 May 24

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Cite this

@article{c7144daed1d84abeba9b50c7fe87dd25,

title = "Challenge of a multiple-valued technology in recent deep-submicron VLSI",

abstract = "A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS passtransistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.",

author = "T. Hanyu",

year = "2001",

month = jan,

day = "1",

language = "English",

pages = "241--244",

journal = "Proceedings of The International Symposium on Multiple-Valued Logic",

issn = "0195-623X",

publisher = "IEEE Computer Society",

note = "31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001) ; Conference date: 22-05-2001 Through 24-05-2001",

}

TY - JOUR

T1 - Challenge of a multiple-valued technology in recent deep-submicron VLSI

AU - Hanyu, T.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS passtransistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.

AB - A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS passtransistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.

UR - http://www.scopus.com/inward/record.url?scp=0034821202&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034821202&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034821202

SP - 241

EP - 244

JO - Proceedings of The International Symposium on Multiple-Valued Logic

JF - Proceedings of The International Symposium on Multiple-Valued Logic

SN - 0195-623X

T2 - 31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001)

Y2 - 22 May 2001 through 24 May 2001

ER -

Challenge of a multiple-valued technology in recent deep-submicron VLSI

Abstract

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this