Challenge of a multiple-valued technology in recent deep-submicron VLSI

T. Hanyu

Challenge of a multiple-valued technology in recent deep-submicron VLSI

T. Hanyu

Systems & Software Division

Research output: Contribution to journal › Conference article › peer-review

5 Citations (Scopus)

Abstract

A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS passtransistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.

Original language	English
Pages (from-to)	241-244
Number of pages	4
Journal	Proceedings of The International Symposium on Multiple-Valued Logic
Publication status	Published - 2001 Jan 1
Event	31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001) - Warsaw, Poland Duration: 2001 May 22 → 2001 May 24

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

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title = "Challenge of a multiple-valued technology in recent deep-submicron VLSI",

abstract = "A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS passtransistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.",

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AB - A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS passtransistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.

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