Building blocks to use in innovative non-volatile FPGA architecture based on MTJs

Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper addresses the need for a non-volatile reconfigurable FPGA in order to allow for many current applications to transition away from costly ASIC development. It is assumed that an architecture has been selected and needs to be filled with blocks designed at the transistor level. These are to allow for non-volatility by means of magnetic tunnel junction devices (MTJs). Circuit level designs are presented, together with their successful simulations. The blocks are therefore assembled together and electrically sound simulations are presented for a fully functional FPGA of minimal size. Design and testing is carried out in Cadance Virtuoso and Spectre along with the IBM p13 toolkit. The typical parameters of a University of Tohoku MTJ are used in a SPICE model developed by University of Minnesota.

Original languageEnglish
Title of host publicationProceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages302-307
Number of pages6
DOIs
Publication statusPublished - 2012 Oct 29
Event2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States
Duration: 2012 Aug 192012 Aug 21

Publication series

NameProceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Other

Other2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
CountryUnited States
CityAmherst, MA
Period12/8/1912/8/21

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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