This paper addresses the need for a non-volatile reconfigurable FPGA in order to allow for many current applications to transition away from costly ASIC development. It is assumed that an architecture has been selected and needs to be filled with blocks designed at the transistor level. These are to allow for non-volatility by means of magnetic tunnel junction devices (MTJs). Circuit level designs are presented, together with their successful simulations. The blocks are therefore assembled together and electrically sound simulations are presented for a fully functional FPGA of minimal size. Design and testing is carried out in Cadance Virtuoso and Spectre along with the IBM p13 toolkit. The typical parameters of a University of Tohoku MTJ are used in a SPICE model developed by University of Minnesota.