Budgeting-free hierarchical design method for large scale and high-performance LSIs

Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes a new hierarchical design method for large scale and high-performance LSIs, which eliminates the need to perform budgeting. The budgeting step in hierarchical design partitions the total propagation time constraint for a path between any two flip-flops (FFs) in different hierarchical blocks into budgets for the different segments of the path that lie within different blocks. In practice, budgeting may result in the need for additional iterations of the synthesis and physical design flow, or may achieve sub-optimal results in terms of area, power, or clock frequency. The proposed method makes the design process budgeting-free by moving the borders of the hierarchical blocks so that all borders of the hierarchical blocks are FFs. For a commercial 500MHz LSI with 141 million transistors, the design team required 2 months to archive the target frequency through try-and-try-again budgeting, while our budgeting-free method produced a design that meets the performance target within days.

Original languageEnglish
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Pages955-958
Number of pages4
DOIs
Publication statusPublished - 2006
Externally publishedYes

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Keywords

  • Budgeting
  • Hierarchical design
  • Physical synthesis

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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