### Abstract

This paper proposes a highly parallel algorithm of separable denominator two‐dimensional (2‐D) state‐space digital filters, called a block parallel algorithm. to derive the block parallel algorithm, the processing image is divided into several blocks and all dependency constraints in a divided block are eliminated. In the block parallel algorithm, the number of multiply‐and‐accumulate operations required to process one image is proportional to 1/L for the block length L. We also study the architecture of the block processor which implements our proposed algorithm. As a result, one 250‐K gates VLSI chip to implement one block processor with the block length L = 8 must be designed. the multiprocessor system comprising 66 proposed VLSI chips can propose 2048 × 2048 pixels image at the rate of 60 frames/s.

Original language | English |
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Pages (from-to) | 20-30 |

Number of pages | 11 |

Journal | Electronics and Communications in Japan (Part III: Fundamental Electronic Science) |

Volume | 78 |

Issue number | 2 |

DOIs | |

Publication status | Published - 1995 Feb |

### Keywords

- Separable denominator two‐dimensional state‐space digital filter
- VLSI implementation
- block parallel algorithm
- highly parallel algorithm
- reduced‐dimensional decomposition

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

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## Cite this

*Electronics and Communications in Japan (Part III: Fundamental Electronic Science)*,

*78*(2), 20-30. https://doi.org/10.1002/ecjc.4430780202