TY - JOUR
T1 - Block parallel architecture of separable denominator two‐dimensional state‐space digital filters based on the reduced‐dimensional decomposition
AU - Iwata, Yasushi
AU - Kawamata, Masayuki
AU - Higuchi, Tatsuo
PY - 1995/2
Y1 - 1995/2
N2 - This paper proposes a highly parallel algorithm of separable denominator two‐dimensional (2‐D) state‐space digital filters, called a block parallel algorithm. to derive the block parallel algorithm, the processing image is divided into several blocks and all dependency constraints in a divided block are eliminated. In the block parallel algorithm, the number of multiply‐and‐accumulate operations required to process one image is proportional to 1/L for the block length L. We also study the architecture of the block processor which implements our proposed algorithm. As a result, one 250‐K gates VLSI chip to implement one block processor with the block length L = 8 must be designed. the multiprocessor system comprising 66 proposed VLSI chips can propose 2048 × 2048 pixels image at the rate of 60 frames/s.
AB - This paper proposes a highly parallel algorithm of separable denominator two‐dimensional (2‐D) state‐space digital filters, called a block parallel algorithm. to derive the block parallel algorithm, the processing image is divided into several blocks and all dependency constraints in a divided block are eliminated. In the block parallel algorithm, the number of multiply‐and‐accumulate operations required to process one image is proportional to 1/L for the block length L. We also study the architecture of the block processor which implements our proposed algorithm. As a result, one 250‐K gates VLSI chip to implement one block processor with the block length L = 8 must be designed. the multiprocessor system comprising 66 proposed VLSI chips can propose 2048 × 2048 pixels image at the rate of 60 frames/s.
KW - Separable denominator two‐dimensional state‐space digital filter
KW - VLSI implementation
KW - block parallel algorithm
KW - highly parallel algorithm
KW - reduced‐dimensional decomposition
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U2 - 10.1002/ecjc.4430780202
DO - 10.1002/ecjc.4430780202
M3 - Article
AN - SCOPUS:0029256444
VL - 78
SP - 20
EP - 30
JO - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
JF - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
SN - 1042-0967
IS - 2
ER -