Bit Cost Scalable technology with and plug process for ultra high density flash memory

H. Tanaka; M. Kido; K. Yahashi; M. Oomura; R. Katsumata; M. Kito; Y. Fukuzumi; M. Sato; Y. Nagata; Y. Matsuoka; Y. Iwata; H. Aochi; A. Nitayama

doi:10.1109/VLSIT.2007.4339708

Bit Cost Scalable technology with and plug process for ultra high density flash memory

H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, A. Nitayama

Center for Innovative Integrated Electronic Systems (CIES)

Research output: Contribution to journal › Conference article › peer-review

401 Citations (Scopus)

Abstract

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Original language	English
Article number	4339708
Pages (from-to)	14-15
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2007.4339708
Publication status	Published - 2007
Event	2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan Duration: 2007 Jun 12 → 2007 Jun 14

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Tanaka, H., Kido, M., Yahashi, K., Oomura, M., Katsumata, R., Kito, M., Fukuzumi, Y., Sato, M., Nagata, Y., Matsuoka, Y., Iwata, Y., Aochi, H., & Nitayama, A. (2007). Bit Cost Scalable technology with and plug process for ultra high density flash memory. Digest of Technical Papers - Symposium on VLSI Technology, 14-15. [4339708]. https://doi.org/10.1109/VLSIT.2007.4339708

Bit Cost Scalable technology with and plug process for ultra high density flash memory. / Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; Katsumata, R.; Kito, M.; Fukuzumi, Y.; Sato, M.; Nagata, Y.; Matsuoka, Y.; Iwata, Y.; Aochi, H.; Nitayama, A.

In: Digest of Technical Papers - Symposium on VLSI Technology, 2007, p. 14-15.

Research output: Contribution to journal › Conference article › peer-review

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AU - Tanaka, H.

AU - Kido, M.

AU - Yahashi, K.

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AU - Katsumata, R.

AU - Kito, M.

AU - Fukuzumi, Y.

AU - Sato, M.

AU - Nagata, Y.

AU - Matsuoka, Y.

AU - Iwata, Y.

AU - Aochi, H.

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