We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 2007|
|Event||2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan|
Duration: 2007 Jun 12 → 2007 Jun 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering