TY - JOUR
T1 - Bit Cost Scalable technology with and plug process for ultra high density flash memory
AU - Tanaka, H.
AU - Kido, M.
AU - Yahashi, K.
AU - Oomura, M.
AU - Katsumata, R.
AU - Kito, M.
AU - Fukuzumi, Y.
AU - Sato, M.
AU - Nagata, Y.
AU - Matsuoka, Y.
AU - Iwata, Y.
AU - Aochi, H.
AU - Nitayama, A.
N1 - Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2007
Y1 - 2007
N2 - We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.
AB - We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.
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U2 - 10.1109/VLSIT.2007.4339708
DO - 10.1109/VLSIT.2007.4339708
M3 - Conference article
AN - SCOPUS:36448932248
SP - 14
EP - 15
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
SN - 0743-1562
M1 - 4339708
T2 - 2007 Symposium on VLSI Technology, VLSIT 2007
Y2 - 12 June 2007 through 14 June 2007
ER -