Bit Cost Scalable technology with and plug process for ultra high density flash memory

H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, A. Nitayama

Research output: Contribution to journalConference articlepeer-review

401 Citations (Scopus)

Abstract

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Original languageEnglish
Article number4339708
Pages (from-to)14-15
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
Publication statusPublished - 2007
Event2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
Duration: 2007 Jun 122007 Jun 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Bit Cost Scalable technology with and plug process for ultra high density flash memory'. Together they form a unique fingerprint.

Cite this