Bit Cost Scalable (BiCS) technology for future ultra high density storage memories

Akihiro Nitayama, Hideaki Aochi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

We proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process. We've applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various memories. The critical scaling issues and the comparison among various 3D-Flash-type memories are to be discussed, as well.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers
Publication statusPublished - 2013 Sep 9
Event2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan
Duration: 2013 Jun 112013 Jun 13

Other

Other2013 Symposium on VLSI Technology, VLSIT 2013
CountryJapan
CityKyoto
Period13/6/1113/6/13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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