Bit Cost Scalable (BiCS) technology for future ultra high density memories

Akihiro Nitayama, Hideaki Aochi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

We proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process. We've applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various memories. The critical issues and the comparison among various 3D NAND Flash-type memories are to be discussed, as well.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
DOIs
Publication statusPublished - 2013 Aug 12
Event2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 - Hsinchu, Taiwan, Province of China
Duration: 2013 Apr 222013 Apr 24

Publication series

Name2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

Conference

Conference2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
CountryTaiwan, Province of China
CityHsinchu
Period13/4/2213/4/24

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Nitayama, A., & Aochi, H. (2013). Bit Cost Scalable (BiCS) technology for future ultra high density memories. In 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 [6545626] (2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013). https://doi.org/10.1109/VLSI-TSA.2013.6545626