Bit Cost Scalable (BiCS) flash technology for future ultra high density storage devices

Akihiro Nitayama, Hideaki Aochi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We have proposed Bit-Cost Scalable (BiCS) technology which realizes a 3D multi-stacked memory array with a few critical lithography steps regardless of the number of stacked layers to keep a drastically continuous reduction of bit cost. The cell array concept, fabrication process, and key features are presented.

Original languageEnglish
Title of host publicationECS Transactions - ISTC/CSTIC 2009 (CISTC)
Pages89-92
Number of pages4
Edition1 PART 1
DOIs
Publication statusPublished - 2009 Dec 1
EventISTC/CSTIC 2009 (CISTC) - Shanghai, China
Duration: 2009 Mar 192009 Mar 20

Publication series

NameECS Transactions
Number1 PART 1
Volume18
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherISTC/CSTIC 2009 (CISTC)
CountryChina
CityShanghai
Period09/3/1909/3/20

ASJC Scopus subject areas

  • Engineering(all)

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