Bit Cost Scalable (BiCS) flash technology for future ultra high density storage devices

Akihiro Nitayama, Hideaki Aochi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

We've developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We've advanced it to Pipe-shaped BiCS flash memory with U-shaped NAND string, improving the operation window and the reliability and realizing the Multi-Level-Cell (MLC) operation. The functionality has been successfully demonstrated using the 32 Gbit test chip with the 16 stacked layers and the MLC operation by 60nm P-BiCS flash technology.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages130-131
Number of pages2
DOIs
Publication statusPublished - 2010 Oct 20
Event2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu, Taiwan, Province of China
Duration: 2010 Apr 262010 Apr 28

Publication series

NameProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Other

Other2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
CountryTaiwan, Province of China
CityHsin Chu
Period10/4/2610/4/28

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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