We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and VOH/VOL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.
|Number of pages||7|
|Journal||IEICE Transactions on Electronics|
|Publication status||Published - 1995 Jul|
ASJC Scopus subject areas
- Electrical and Electronic Engineering