Benchmarks for FPGA-Targeted High-Level-Synthesis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently, high-level synthesis (HLS) tools such as 'Intel FPGA SDK for OpenCL" and 'Xilinx SDAccel' have been introduced to design FPGA accelerators. Those HLS tools use 'C language' based environment to significantly reduce the design time. However, it is also important to know how much performance we can achieve using HLS tools. FPGA is a highly reconfigurable hardware and the performances are extremely different depending on the architecture. Performances also depend on the FPGA board, HLS software and firmware such as BSP (board support package). Therefore, benchmarking FPGAs is an extremely challenging task. This paper proposes a method to design benchmarks for FPGA-targeted HLS. The benchmarks are highly scalable and can be used for different FPGAs and compilers to obtain most of the potential performance. Evaluating four different FPGAs, we found that the single-precision floating-point computation performance varies from 17 GFLOPS to 3,955 GFLOPS depending on the operation and the FPGA. We have obtained 64% and 43% of the peak performance of single-precision computation for Arria 10 and Stratix 10 FPGAs respectively. The fixed-point computation performance heavily depends on the bit size and varies from 8 GOPS to 12,800 GOPS.

Original languageEnglish
Title of host publicationProceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages232-238
Number of pages7
ISBN (Electronic)9781728147253
DOIs
Publication statusPublished - 2019 Nov
Event7th International Symposium on Computing and Networking, CANDAR 2019 - Nagasaki, Japan
Duration: 2019 Nov 262019 Nov 29

Publication series

NameProceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019

Conference

Conference7th International Symposium on Computing and Networking, CANDAR 2019
CountryJapan
CityNagasaki
Period19/11/2619/11/29

Keywords

  • FPGA accelerator
  • High performance computing
  • High-level synthesis
  • Performance tuning

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Networks and Communications
  • Hardware and Architecture
  • Signal Processing

Fingerprint Dive into the research topics of 'Benchmarks for FPGA-Targeted High-Level-Synthesis'. Together they form a unique fingerprint.

Cite this