Recent high-performance microprocessors have two or more functional units (FUs) to exploit instruction-level parallelism. To make full use of this capability, multiport register files are generally used. However, conventional multiport register files need a considerable amount of hardware. This paper proposes a multiport register file scheme, which uses time-division multiplexing with wave pipelining in order to save the needed hardware resources. For adjusting propagation delay timings, we develop a tool which automatically inserts dummy buffers into combinatorial logic.
|Number of pages||6|
|Publication status||Published - 1998 Dec 1|
|Event||Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn|
Duration: 1998 Feb 10 → 1998 Feb 13
|Other||Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)|
|Period||98/2/10 → 98/2/13|
ASJC Scopus subject areas