Automated design of wave pipelined multiport register files

Kouji Takano; Takehito Sasaki; Nobuyuki Oba; Hiroaki Kobayashi; Tadao Nakamura

Automated design of wave pipelined multiport register files

Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura

INF - Computer and Mathematical Sciences

Research output: Contribution to conference › Paper › peer-review

Abstract

Recent high-performance microprocessors have two or more functional units (FUs) to exploit instruction-level parallelism. To make full use of this capability, multiport register files are generally used. However, conventional multiport register files need a considerable amount of hardware. This paper proposes a multiport register file scheme, which uses time-division multiplexing with wave pipelining in order to save the needed hardware resources. For adjusting propagation delay timings, we develop a tool which automatically inserts dummy buffers into combinatorial logic.

Original language	English
Pages	197-202
Number of pages	6
Publication status	Published - 1998 Dec 1
Event	Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn Duration: 1998 Feb 10 → 1998 Feb 13

Other

Other	Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
City	Yokohama, Jpn
Period	98/2/10 → 98/2/13

ASJC Scopus subject areas

Engineering(all)

Cite this

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author = "Kouji Takano and Takehito Sasaki and Nobuyuki Oba and Hiroaki Kobayashi and Tadao Nakamura",

year = "1998",

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AU - Takano, Kouji

AU - Sasaki, Takehito

AU - Oba, Nobuyuki

AU - Kobayashi, Hiroaki

AU - Nakamura, Tadao

PY - 1998/12/1

Y1 - 1998/12/1

N2 - Recent high-performance microprocessors have two or more functional units (FUs) to exploit instruction-level parallelism. To make full use of this capability, multiport register files are generally used. However, conventional multiport register files need a considerable amount of hardware. This paper proposes a multiport register file scheme, which uses time-division multiplexing with wave pipelining in order to save the needed hardware resources. For adjusting propagation delay timings, we develop a tool which automatically inserts dummy buffers into combinatorial logic.

AB - Recent high-performance microprocessors have two or more functional units (FUs) to exploit instruction-level parallelism. To make full use of this capability, multiport register files are generally used. However, conventional multiport register files need a considerable amount of hardware. This paper proposes a multiport register file scheme, which uses time-division multiplexing with wave pipelining in order to save the needed hardware resources. For adjusting propagation delay timings, we develop a tool which automatically inserts dummy buffers into combinatorial logic.

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T2 - Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)

Y2 - 10 February 1998 through 13 February 1998

ER -

Automated design of wave pipelined multiport register files

Abstract

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ASJC Scopus subject areas

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