Automated design of wave pipelined multiport register files

Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura

Research output: Contribution to conferencePaperpeer-review

Abstract

Recent high-performance microprocessors have two or more functional units (FUs) to exploit instruction-level parallelism. To make full use of this capability, multiport register files are generally used. However, conventional multiport register files need a considerable amount of hardware. This paper proposes a multiport register file scheme, which uses time-division multiplexing with wave pipelining in order to save the needed hardware resources. For adjusting propagation delay timings, we develop a tool which automatically inserts dummy buffers into combinatorial logic.

Original languageEnglish
Pages197-202
Number of pages6
Publication statusPublished - 1998 Dec 1
EventProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
Duration: 1998 Feb 101998 Feb 13

Other

OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
CityYokohama, Jpn
Period98/2/1098/2/13

ASJC Scopus subject areas

  • Engineering(all)

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