Atomically flattening technology at 850°C for Si(100) surface

X. Li, T. Suwa, A. Teramoto, R. Kuroda, S. Sugawa, T. Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

We demonstrate a low temperature flattening method for the 200-mm-diameter (100) orientation silicon wafers. By annealing in ultra pure argon ambient at 850°C or above, atomically flat surfaces composed of atomic terraces and steps appear uniformly in the whole 200mm wafer. The width of atomic terrace changes with the off angle of wafer surface. It is found that with the off angle of 0.50° or below, only mono-atomic steps appear on the atomically flat surface, and the terrace widths are almost equal to the calculation values. Moreover, we have found using the vertical furnace the whole 200mm wafer surface can be atomically flattened in shorter time by increasing the argon gas flow rate or the annealing temperature. Furthermore, after annealing at 900°C or below, there is no slip-line defect in the whole wafer. This low temperature flattening method is very suitable to be applied in the LSI manufacturing.

Original languageEnglish
Title of host publicationAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6
Subtitle of host publicationNew Materials, Processes, and Equipment
Pages299-309
Number of pages11
Edition1
DOIs
Publication statusPublished - 2010 Dec 30
EventAdvanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting - Vancouver, BC, Canada
Duration: 2010 Apr 262010 Apr 27

Publication series

NameECS Transactions
Number1
Volume28
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherAdvanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting
CountryCanada
CityVancouver, BC
Period10/4/2610/4/27

ASJC Scopus subject areas

  • Engineering(all)

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