Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

Tetsuya Goto, Rihito Kuroda, Naoya Akagawa, Tomoyuki Suwa, Akinobu Teramoto, Xiang Li, Toshiki Obara, Daiki Kimoto, Shigetoshi Sugawa, Tadahiro Ohmi, Yutaka Kamata, Yuki Kumagai, Katsuhiko Shibusawa

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10 Citations (Scopus)


By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trenchisolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22μm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate-source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

Original languageEnglish
Article number04DA04
JournalJapanese journal of applied physics
Issue number4
Publication statusPublished - 2015 Apr 1

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)


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