Atomically flat interface for noise reduction in SOI-MOSFETs

Philippe Gaubert, Alexandre Kircher, Hyeonwoo Park, Rihito Kuroda, Shigetoshi Sugawa, Tetsuya Goto, Tomoyuki Suwa, Akinobu Teramoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

New process conditions involving temperature below 900°C, and then compatible with SOI wafers and CMOS technologies, were successfully developed in order to realize atomic flat interface in MOSFETs. The implementation of these processes did not only reduce the variability of electrical performances but also brought the low frequency noise level down, making MOSFETs fabricated on atomically flat surfaces superior to non processed MOSFETs in all aspects. The newly developed low-temperature atomic flat process is paving the way to high-performance high-reliability and low-noise MOSFETs for the realization of the next VLSI on SOI technology.

Original languageEnglish
Title of host publication2017 International Conference on Noise and Fluctuations, ICNF 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509027606
DOIs
Publication statusPublished - 2017 Jul 19
Event2017 International Conference on Noise and Fluctuations, ICNF 2017 - Vilnius, Lithuania
Duration: 2017 Jun 202017 Jun 23

Publication series

Name2017 International Conference on Noise and Fluctuations, ICNF 2017

Other

Other2017 International Conference on Noise and Fluctuations, ICNF 2017
CountryLithuania
CityVilnius
Period17/6/2017/6/23

Keywords

  • MOSFET
  • RTN
  • SOI
  • atomic
  • electron
  • flat
  • interface
  • low frequency noise
  • process
  • temperature

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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